Risc and CISC Languages Essay

Paper Type:  Essay
Pages:  2
Wordcount:  466 Words
Date:  2022-04-04

Design alternatives provide powerful operations with a goal of reducing the number of instructions that are being executed at the same time. The danger associated with the slower cycle time or a higher cipher is executed. Some of the instructions provided by CISC processors are so esoteric that many compilers simply do not attempt to use them. In fact, many of these instructions can only be utilized through a carefully handwritten assembly program. Even if such powerful instructions could be used by compilers, it is difficult to imagine that they would be used very frequently. Common sense tells us that useless (or seldom used) instructions should not be added to the instruction set.

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This basic concept of not adding useless instructions to the instruction set has invoked an increasing interest in an innovative approach to computer architecture, the reduced instruction set computer (RISC). The design philosophy of the RISC architecture says to add only those instructions to the instruction set that result in a performance gain. RISC systems have been defined and designed by different groups in a variety of ways.

Computer designers have different viewpoints, but the following two criteria are universally accepted goals for all systems: To maximize speed of operation or minimize execution time and to minimize development cost and sale price. Several factors are involved when discussing RISC advantages: computing speed, VLSI realization, design time cost, reliability, and high-level language support. As for computing speed, the RISC design is suited more elegantly to the instruction pipeline approach. An instruction pipeline allows several instructions to be processed at the same time. The process of an instruction is broken into a series of phases, such as instruction fetch, instruction decoding, operand fetch, execution, and write back. While an instruction is in the fetch phase, another instruction is in decoding phase, and so on. The RISC architecture maximizes the throughput of this pipeline by having uniform instruction size and duration of execution for most instructions. Uniform instruction size and execution duration reduce the idle periods in the pipeline. Another advantage of RISC is that it requires a shorter design period.

The time taken for designing a new architecture depends on the complexity of the architecture. Naturally, the design time is longer for complex architectures (CISCs), which require debugging of the design and removal of errors from the complex microprogrammed control unit. In the case of RISC, the time taken to test and debug the resulting hardware is less because no microprogramming is involved and the size of the control unit is small. A shorter design time decreases the chance that the end product may become obsolete before completion. A less complex architecture unit has less chance of design error and therefore higher reliability. Thus the RISC design yields cheaper design costs and design reliability benefits.

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