Digital Logic in the Physical World: Challenges and Solutions - Research Paper

Introduction

Implementing digital logic in the physical world is often difficult, as the real world rarely presents data in a digital construct. There are, however, several methods and devices that will allow this data to be used. Any information gathered would first have to be converted using an analog to the digital signal converter; once done, the signal can then be fed into one of the available options to process the data as mentioned above. One of the most widely used devices used for the processing of this data is the FPD or the programmable field device. Field programmable devices are, as defined by the book, "digital integrated circuits capable of being programmed to provide a variety of different logic functions." This broad category of devices is part of what makes many of the complex functions of our modern world possible. These devices have seen use from high-speed trading on the stock market, and medical imaging to signal processing in cell towers. They are used in so many applications, due to their high speed and ability to process multiple signals in parallel.

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FPDs are combinational circuits composed of arrays of logic gates. These circuits process data by using switching elements to route the data to the correct array to be ANDed, ORed, XORed, and Inverted, or any combination of these gates. These gates are arranged into multiplexers that act as signal selectors based on a second input signal. While these are the primary components, there are other components contained in FPDs that are crucial to their operation, flip-flops and clocks allow the signal to move forward at a predictable and consistent pace.

FPDs can be broken down into several categories: SPLDs, simple programmable logic devices, simple arrays of gates, often two levels, containing AND and OR arrays; CPLDs, sophisticated programmable machines, which are composed of arrangements of SPLDs; and FPGAs, field-programmable gate arrays, which is an advanced device that contains the elements of the previous devices but is programmable by the end-user, through the use of LUTs, lookup tables. The use of LUTs allows the end-user to change the function of the FPGA by rerouting the signal and adjusting the multiplexer selection values. The programmability of some logic devices, like the FPGA, has allowed their use to grow significantly because it allowed increased flexibility and expansive use cases.

The use of this technology has been growing substantially since its introduction in the 1970s and its continued refinement. The main driver of this growth is the signal processing speed and ability to process multiple signals in parallel. In modern computer processors, instructions are processed sequentially, in the order defined by the operating system; however, logic devices can process and combine multiple signals into a single signal concurrently or can process multiple independent signals to independent outputs without affecting the speed elsewhere on the device. This parallelism is one of the tremendous benefits of logic devices and why it has become so ubiquitous in the technology landscape.

As the circuits have increased in complexity, so has the design process. Designing a logic circuit, whether to be manufactured or implemented on an FPGA, entails several steps to get from idea to functional device. The first step starts with defining the schematics, inputs, and outputs in a CAD program for logic devices. Another option is to identify and describe the circuit using the HDL, hardware description language. Once designed, the CAD program will then take that design and optimize the logic through the use of algorithms to reduce required gates to its purest form. This simplified circuit goes through the process of fitting as the CAD software determines the most efficient method and interconnects to use on the final product. Afterword, additional algorithms will analyze the output and simulate the circuit to determine if it is operating as designed. At each step, the design is often refined and updated to take advantage of the information provided by the simulation. Once the design is complete, the information is prepared for programming to the logic device using a specially designed programming device.

Through the years, many improvements and refinements have yielded a multitude of logic devices, some for specific purposes, while others are more general and versatile. Logic devices are, at their core, composed of simple devices. Still, they have been implemented with layers of complexity that have increased their function, which has allowed for their use in many novel implementations. As the use of logic devices increased, their functions allowed us to push the technological boundaries of science, medicine, and communications, by providing a means for the processing of real-world data, in real-time. This project focuses on future and current electronic-based systems that can benefit from (Field-Programmable Gate Array). Design flows, trends, and tools shall be explicitly explained together with research issues currently investigated.

Digital Programmable Devices technology

Since the introduction of these devices in the 1970s, the PLD (Programmable Logic Devices) developed from the implementation from small to large SoC (Configurable multi-processor systems on chip). The most renowned PLD technology today is referred to as Field programmable gate array (FPGA), which primarily used in domain applications, including the industry of Telcom. However, modern market researches indicate a consistent demand for these sophisticated microelectronic devices in the future. But for medium and small businesses or SME dominated states such as Austria, (Field-Programmable Gate Array) can be accessible to enormous scale integration by preventing higher non-recurring engineering costs of application-specific integrated circuits(ASICs). However, for the colossal circuits, which may be due to complexity cannot be handled by the CPLD, the PALs instead of the extended PLDs shall be somehow appropriate. Their architectures are structurally elaborate and more sizeable compared to; thus, it takes minimal time for one to comprehend them. The primary distinction is the incorporation of the kind of the devices of interconnecting matrices significantly permitting the interconnection of about four PAL on a single chip rather than four individual on a printed circuit board. Logically, this seems inconsequential even though the increased efficiency of this particular device is in a manner that more useful tools are required for its proper utilization, most specifically the interconnect matrix. The route and place problems that might emerge can be wholly ignored in the programmable course if deemed inappropriate (Bui, van, Thi Hieu & Minh 10).

The loss of management over the real implementation of the digital programmable devices might be discouraging to the individual student designer but should instead be considered as an epitome of the unavoidable trade-offs which continuously have to be established in the design technologies. A comprehensive distinction can be seen in the in-system and out-of-system re-programmability. In system, reprogrammable needs a static ram depending on the architecture or power loss or rather loss of function. However, for the most sophisticated devices like SRAM based field programmable gate design arrays, there exist a way of downloading retrieved from on-board PROM that eliminates the issue. The non-SCRAM devices possess programming times that are of several orders of larger magnitudes; hence once inserted into the system, they mostly have one functionality. The mechanisms of this type are either electronically alterable or UV-erasable; thus need more hardware for programming and must be detached from the circuit for the reprogramming.

FPGA Design Flow

Field programmable gate arrays (FPGA), are those devices included in a consistent evolution to provide many features and somewhat better performance and their superior functionality include :Flexible architecture is comfortably adaptable to every application (Carter &William 11).

The mass capacity of integration which permits the implementation of sophisticated digital systems in one circuit.Have particular digital resources for the generation of the internal memory units.

The capacity to transform the block role in actual time; reconfigurability.

Produce adaptive circuits.

Has the capacity to operate multiple applications independently- the description of hardware programming.

Field programmable gate array (FPGA), have usually ceased being simple architecture since they represent some robust integrated systems with numerous possibilities and various families to consider. In the previous decades, Field programmable gate array (FPGA), which primarily used in domain applications, Field programmable gate array had manifested a vital evolution from the initial critical change which was conducted when the family of Virtex II appeared in the year 2001 focusing on the LUT(LOOKUP TABLES) to the recent technologies. It is, therefore, critical to acknowledge Field programmable gate array internal programming architecture to create more of their advantages. This could be based on performance, marketing time, prize, reliability, and maintenance (Bui et al. 10).

Additionally, the other essential features of the Virtex II device is derived from its ability to reflect many eighteen Kb block random assessment memories. These memories are the actual RAM dual-port providing fast, discrete, and huge blocks of memories in a device. They are arranged in columns, and the entire amount depends on the size of Virtex II devices. Also, it was created by the distribution of RAM blocks and efficient performance interface with an eternal memory like DDR SDRAM, QDR SRAM, and ZBT SRAM (Carter &William 13).

The other attractive characteristic in Virtex II Field programmable gate array was the committed eighteen times eighteen bits multiplier of hardware that permitted allowed the creation of MAC function. These particular modules make it possible to execute two's supplement operations.

On the virtual II clock circuit, every Field programmable gate array has sixteen global clock multiplexors that control the signal of the clock offered ROM he inputs port, the DCM (Digital clock manager), or interconnection of local line. The digital block managers are offered by the terminals of the external input and permit the Field programmable gate array to amplify ad delay the signal of the clock.

Those Field programmable gate array models connect with some other systems either through input or output IOB blocks that depend on four and two output and input flip-flop consecutively, as indicated in the figure below. The IOB blocks contain a digital management impedance that is DCI, which permits the Field programmable gate array to establish a configurable impedance output to adapt it to the PCB track, which shall eventually be connected.

Besides, it is also possible for the configuration of the terminals to be compatible with the transmitters and receivers in their individual Field programmable gate array to improve the integrity of the signal and the suppression of the reflections (Johnson 9).

The other evolution accompanied the Virtex IV and V models since they implemented the committed processors of digital signal DSPs that makes it possible to execute more sophisticated calculations with excellent performance (Meyer-Baese et al. 7). They involve improvements like:

• FIFOs
• TEMAC
• Regional clock buffer
• Mul...